The present invention relates to the structure of a semiconductor device and a method of manufacturing the device, in particular, to a technique effective when applied to a semiconductor device including a fin transistor.
There is proposed an electric field effect transistor having a protruding semiconductor layer, that is, a layer protruding upward from the plane of a substrate and having a channel region on at least both planes (both side surfaces) substantially perpendicular to the plane of the substrate (which transistor will hereinafter be called “fin electric field effect transistor and abbreviated as “FinFET”) in order to reduce a short channel effect which will be caused by miniaturization.
The FinFET is shaped to have a three dimensional structure on a two dimensional substrate. Supposing that the area of the substrate is equal, this transistor has current driving ability greater than that of a planar transistor. Since a gate has a structure of wrapping a channel therein, the gate has high channel controllability and a leakage current at the time when the device is OFF is reduced largely. It is therefore possible to actualize an electric field transistor having a high operation rate, driven at low power consumption, and facilitating provision in a miniaturized form.
As an electrically programmable and erasable nonvolatile semiconductor memory device, EEPROM (electrically erasable and programmable read only memory) has been used widely. This memory device typified by flash memory which is popular now stores data by providing a charge accumulation region in the gate insulating film of a MISFET and making use of a nonvolatile change of a threshold voltage attributable to the region. Readout is performed by determining the threshold voltage from the channel current value of the MISFET. Accumulation of charges is actualized using a floating gate electrode surrounded with an insulating film or a trap level in the insulating film.
As this flash memory, there is a split gate cell using a MONOS (metal oxide nitride oxide semiconductor) film. This split gate MONOS is characterized by that it can actualize high charge retention characteristics (reliability) because of trapping of charges in a SiN film and high-speed and low-power-consumption readout because of using a thin-film gate oxide film for a control gate.
The present inventors have been engaged in research and development of semiconductor devices having a nonvolatile memory cell as described above and they are now developing a split gate type Fin-MONOS device.
As the background technique in this technical field, there is, for example, a technique of Patent Document 1. Patent Document 1 discloses a split gate MONOS memory comprised of a FinFET.